The present invention relates to a method of forming damascene patterns of semiconductor devices and, more particularly, to a method of forming damascene patterns of semiconductor devices, which is capable of forming damascene patterns having a uniform depth.
Semiconductor memory devices are classified into volatile memory in which data is lost when power is off and nonvolatile memory in which data can be retained although power is off.
Nonvolatile memory may include Erasable Programmable Read Only Memory (EPROM), Electrically Erasable Programmable Read Only Memory (EEPROM), flash memory, and so on.
Flash memory among the nonvolatile memory devices refers to devices in which data can be retained although power is off and which can be electrically programmed and erased without a refresh function of rewriting data at specific intervals. Here, the terminology ‘program’ refers to an operation of writing data into memory cells, and the terminology ‘erase’ refers to an operation of erasing data written into memory cell.
The flash memory devices are divided into NOR type flash memory devices and NAND type flash memory device depending on a structure and operating conditions of a cell. In the NOR type flash memory devices, a drain of each of memory cell transistors is connected to bit lines, thus enabling program and erase for a specific address. Accordingly, the NOR type flash memory devices are generally used for applications requiring a high-speed operation because the operating speed is fast. In contrast, in the NAND type flash memory devices, a plurality of memory cell transistors is connected in series, constituting one string, and one string is coupled between bit lines and a common source line. Thus, the NAND type flash memory device has a relatively small number of drain contact plugs, thus facilitating the higher integration. Accordingly, the NAND type flash memory devices are generally used for applications requiring high-capacity data retention.
Each of the NAND type flash memory devices includes a plurality of word lines formed between a source select line and a drain select line. Select lines may include, for example, source select lines or drain select lines. A junction is formed between each of the select lines and each of the word lines. A junction between the source select lines is a common source region, and a junction between the drain select lines is a drain region.
Typically, a gate and a drain region are electrically brought in contact with the outside through contact holes, but a common source region is electrically brought in contact with the outside through a common source line having a line structure. Accordingly, the common source line occupies a large area in a flash memory device. In order to improve the performance of a flash memory device, many attempts are made to decrease the sheet resistance of the common source line. This becomes a more important issue as semiconductor devices gradually reduce in size and have higher integration.